The present invention relates to flash memory or EEPROM memory cells using isolated gate floating gates.
Flash memory cell arrays using isolated gate floating gate MOSFET transistors store charge on the floating gates which modify the threshold voltage (xe2x80x9cVtxe2x80x9d) of the MOSFETs of the memory cells. These memory cells can be arranged in a NAND gate or NOR gate architecture for purposes of reading and writing the respective cells in the array.
To achieve higher density, the feature size of these cells is currently at a low sub-micron level. As the channels of these transistors become shorter, a number of detrimental short channel effects are seen. One solution to avoid these effects, such as xe2x80x9cpunch-throughxe2x80x9d, is to reduce the dopant levels of the source and drain of the MOS devices. Reducing source and drain dopant levels, however, cause an increase in the series resistance of a memory cell device, thus reducing the read current to an unacceptably low level.
There is thus a need for a method and an apparatus that maintain a sufficiently high read current in a floating gate MOSFET transistor, even with a reduced source and drain dopant levels. In the past, retrograde doping distribution are created by ion implantation and subsequent annealing to modify the underlying p-type or n-type well dopant concentration. Such a process is described in Yang, Microelectronic Devices, McGraw-Hill, 1988, and U.S. Pat. No. 5,045,898, issued to Chen et al. on Aug. 30, 1991, entitled CMOS INTEGRATED CIRCUIT HAVING IMPROVED ISOLATION, and U.S. Pat. No. 5,091,332, issued to Bohr et al. on Feb. 25, 1992, entitled SEMICONDUCTOR FIELD OXIDATION PROCESS, the disclosures of which are hereby incorporated by reference. Retrograde dopant distribution in the channel region has also been used to create buried n-channel devices (PMOS) to deal with short channel effects, as is shown in U.S. Pat. No. 5,122,474, issued to Harrington III on Jun. 16, 1992, entitled METHOD OF FABRICATING A CMOS IC WITH REDUCED SUSCEPTIBILITY TO PMOS PUNCHTHROUGH, the disclosure of which is hereby incorporated by reference.
Other methods addressing punch-through and other short-channel effects have included buried back gates, as shown in U.S. Pat. No. 5,877,049, issued to Liu et al. on Mar. 2, 1999, entitled METHOD FOR FORMING ADVANCED TRANSISTOR STRUCTURES WITH OPTIMUM SHORT CHANNEL CONTROLS FOR HIGH DENSITY HIGH PERFORMANCE INTEGRATED CIRCUITS, the disclosure of which is hereby incorporated by reference.
The present invention relates to providing dopant in the channel area of a well structure for NAND type memory cells formed by isolated gate floating gate transistors. The dopant is provided by ion implantation with a tilt angle around the existing floating gate structure at a selected stage of the fabrication process following the formation of the control/floating gate structure. The process of the present invention may occur before or after the implantation of the source and drain dopants. The tilt angle implantation forms a retrograde distribution from the channel surface, which is also concentrated laterally toward the centerline axis of the gate structure and decreases towards the opposing source and drain regions. This retrograde distribution promotes buried-channel-like performance of the transistors connected in series in the NAND gate memory architecture and reduces series resistance of the series-connected floating gate MOS devices. Consequently, a reduction in source/drain dopant levels is achieved. Decreasing the series resistance in the bit line provides higher the output current that is available for sensing for a given selected Vcc.